1. Technical Field
The present invention relates to a semiconductor memory device, and in particular, to a semiconductor memory device that uses a bit line precharge method.
2. Related Art
In a semiconductor memory device such as a memory or the like, generally, there are cases in which various types of leakage current arise at the interior of the semiconductor memory device. Due to leakage current arising, problems such as an increase in consumed electric power, and the like, arise.
Therefore, there are techniques that suppress leakage current. For example, Japanese Patent Application Laid-Open (JP-A) No. 2006-040431 discloses a technique of suppressing an increase in consumed electric power by suppressing sub-threshold current of a MOSFET, that is leakage current that arises in a semiconductor integrated circuit device such as an SRAM (static RAM) that is a volatile memory, or the like.
Further, JP-A No. 2006-228294 discloses a technique of reducing consumed electric power by reducing leakage current that flows from bit lines into memory cells due to precharging of the bit lines at the time of accessing the memory cells, which current is leakage current that arises in a semiconductor memory device using a bit line precharge method such as an SRAM or the like.
On the other hand, there are cases in which leakage current, that flows into bit lines from signal lines that are for outputting, to the exterior, signals (stored data) that are read-out from memory cells, arises in a semiconductor memory device.
FIG. 3 illustrates an example of the schematic structure of a NAND-type mask ROM that is a non-volatile memory, as a concrete example of a semiconductor memory device that uses a conventional bit line precharge method.
A conventional semiconductor memory device 100 is structured to include an input buffer circuit 112, a control circuit 114, a row decoder circuit 116, a column decoder circuit 118, a memory cell array 120, a bit line selection circuit 122, and an AMP circuit 124.
The memory cell array 120 includes (m+1)×(n+1) NMOS transistors 130, that are arrayed in m+1 rows and n+1 columns and structure memory cells, and m+1 NMOS transistors 131 for precharging. Note that, when referring to the NMOS transistors 130 generically without distinguishing among the individual transistors, they are simply called the NMOS transistors 130, and when designating the NMOS transistor 130 that is disposed in the ith row and the jth column, it is called the NMOS transistor 130<i,j>. Similarly, when referring generically to the NMOS transistors 131 for precharging, they are simply called the NMOS transistors 131 for precharging, and when designating the NMOS transistor 131 for precharging that is disposed in the jth column, it is called the NMOS transistor 131<j> for precharging.
The bit line selection circuit 122 is for selecting any one of bit lines BL<0> through BL<m> on the basis of inputted bit line selection signals V<0> through V<m>, and includes m+1 bit line selection circuits 123.
An external control signal/PC that is inputted from the exterior of the semiconductor memory device 100 is inputted to the control circuit 114 via the input buffer circuit 112. In accordance with the inputted external control signal/PC, the control circuit 114 generates a bit line precharge control signal preb that is a control signal for precharging the bit line BL, and outputs the bit line precharge control signal preb to the NMOS transistor 131 for precharging and to the gate of a PMOS transistor 144 for precharging the bit line BL.
At the PMOS transistor 144, the source is connected to a power supply, and the drain is connected to a data line data for outputting data signals from the bit line selection circuit 123 to the AMP circuit 124. When the bit line precharge control signal preb is “L” level, the PMOS transistor 144 is in an on state, and, by applying voltage to the data line data, precharges the one bit line BL that is selected by the bit line selection circuit 123.
An external address signal ADD that is inputted from the exterior of the semiconductor memory device 100 is inputted to the row decoder circuit 116 and the column decoder circuit 118 via the input buffer circuit 112.
On the basis of the inputted external address signal ADD, the row decoder circuit 116 generates word line signals WL<0> through WL<n>, and outputs them from respective word lines WL<0> through WL<n> to the memory cell array 120. The word line signals WL<0> through WL<n> express non-selection when “H” level, and express selection when “L” level.
The word lines WL<0> through WL<n> are connected to the gates of the NMOS transistors 130 of the memory cell array 120. At the NMOS transistor 130 whose source and drain are shorted, current flows from the drain to the source even when the word line signal WL is “L” level. On the other hand, at the NMOS transistor 130 whose source and drain are not shorted, current does not flow when the word line signal WL is “L” level.
On the basis of the inputted external address signal ADD, the column decoder circuit 118 generates the bit line selection signals V<0> through V<m>, and outputs them from bit line selection lines V<0> through V<m> to the corresponding bit line selection circuits 123 of the bit line selection circuit 122.
The bit line selection circuit 122 has the bit line selection circuit 123 for each of the bit lines BL, and, on the basis of the inputted bit line selection signals V<0> through V<m>, selects the one of the bit lines BL<0> through BL<m> that corresponds to the address, and connects the selected bit line to the AMP circuit 124.
The reading-out operations of the conventional semiconductor memory device 100 are described next. FIG. 4 is an example of a timing chart of the reading-out operations at the semiconductor memory device 100. Note that FIG. 4 shows, as a concrete example, a case in which the external address signal ADD instructs address <0,0> (a case in which the address <0,0> is read-out).
The external control signal/PC is inputted from the exterior to the input buffer circuit 112. When the external control signal/PC is inputted from the input buffer circuit 112, the control circuit 114 generates the bit line precharge control signal preb. When the bit line precharge control signal preb is “L” level, the gate of the PMOS transistor 144 is turned on, and is precharged, and the data line signal data becomes “H” level. Further, the gate of the NMOS transistor 131 for precharging turns off.
The one bit line BL<0> through BL<m>, that is selected by the external address signal ADD that was inputted from the exterior to the column decoder circuit 118 via the input buffer circuit 112, is precharged to “H” level. FIG. 4 shows a case in which the bit line selection signal V<0> is “H” level, the bit line selection signals V<1> through V<m> are “L” level, and the bit line BL<0> is selected.
Further, one of the word line signals WL<0> through WL<n> is selected at the row decoder circuit 116 in accordance with the external address signal ADD. FIG. 4 shows a case in which the word line signal WL<0> is “L” level, the word line signals WL<1> through WL<n> are “H” level, and the word line signal WL<0> is selected. When the external control signal/PC becomes “H” level, the precharging operation finishes, and the reading-out operation starts.
Because the source and the drain of the NMOS transistor 130<0,0> are not shorted, current does not flow to the NMOS transistor 130<0,0>, and the bit line signal BL<0> is maintained at “H” level. Accordingly, an external output signal OUTD that is outputted from the AMP circuit 124 is “L” level.
However, when the time period over which the external control signal/PC is “H” level becomes long, there is the problem that, due to leakage current that flows-in from the data line signal data to the bit line signal BL, the precharge level of the data line signal data cannot be maintained, the output level of the external output signal OUTD inverts, and malfunctioning occurs.
In the state in which the bit line selection signal V<0> is “H” level and the bit line selection signals V<1> through V<m> are “L” level, at the bit line selection circuit 123<0>, an NMOS transistor 134<0> that is connected to the data line data and the bit line BL<0> is in an on state, and an NMOS transistor 136<0> is in an off state. On the other hand, at the bit line selection circuits 123<1> through 123<m>, the NMOS transistors 134<1> through 134<m> are in off states, and the NMOS transistors 136<1> through 136<m> are in on states.
At the NMOS transistors 134<1> through 134<m> of the bit line selection circuits 123<1> through 123<m>, because the data line signal data is “H” level and the bit line signals BL<1> through BL<m> are “L” level, leakage current arises due to the potential difference between the both. Namely, leakage current flows from the data line data into the bit lines BL<1> through <m>. When, due to the occurrence of leakage current, the potential of the data line signal data decreases and the bit line signal BL<0> cannot maintain the precharge level (“H” level) and the voltage of the data line signal data falls below the threshold value of the AMP circuit 124, the level of the external output signal OUTD inverts from “L” level to “H” level, and malfunctioning occurs. In FIG. 4, when timing t is reached, due to the drop in the voltage of the data line signal data, the signal level of the external output signal OUTD inverts and malfunctioning occurs.
In particular, when the number m of rows becomes large, the number of bit line selection circuits 123 at which leakage current is generated also becomes large, and therefore, the leakage current increases. Thus, it is easy for the voltage of the data line signal data to decrease to below the threshold value of the AMP circuit 124, and it is easy for malfunctioning to occur.